A differential input stage in some circuit applications can be susceptible to latch-up when power is disabled to the overall circuit but input signals are applied to the differential input stage. For example, the differential input stage may be part of an operational amplifier in a battery-operated device that is turned off and being recharged. In this example, the differential input stage includes an emitter-coupled pair coupled to a current mirror formed from bipolar transistors of conductivity opposite that of the emitter-coupled pair. In particular, each collector of the emitter-coupled pair is connected to an emitter of a corresponding bipolar transistor of the current mirror. The bases of the emitter-coupled pair are connected to receive the differential input signal.
Thus, for example, if the emitter-coupled pair is implemented with NPN transistors, the collectors of the emitter-coupled pair are connected to emitters of corresponding PNP transistors of the current mirror. This configuration is typically used to achieve full VCC-rail sensing of the differential input signal. The path from the base to the collector of one of the NPN transistors of the emitter coupled pair, and on to the emitter and base of the corresponding PNP transistor form a PNPN structure (i.e., similar to a silicon controlled rectifier or SCR) susceptible to latch-up. This PNPN structure can become forward biased in certain conditions. For example, if the power is off but a voltage is present across the bases of the emitter-coupled pair (which can arise when a battery-operated device is turned off or is turn-off and being recharged), the PNPN structure becomes forward biased. As is well known, once a SCR is turned on (i.e., one of the PN junctions becomes forward biased) and conducting at least a threshold current, the SCR is latched into a conductive state and, in general, can only be turned off by reducing the current through the SCR using an external circuitry. Thus, if the current through the PNPN structure is large enough, the PNPN structure is turned on, thereby causing latch-up.
In some implementations, the current mirror includes load resistors formed in a P-type well in an N-type tub. Each load resistor is connected between a PNP current mirror transistor and the VCC bus. Thus, another PNPN structure can be formed from the base to the collector of one of the NPN transistors of the emitter-coupled pair, to the P-type well of the load transistor and on to the N-type tub. Accordingly, there is a need for a differential input stage that provides full-rail sensing and reduces both latch-up susceptibility and power dissipation.
In accordance with aspects of the present invention, a differential input stage with full-rail sensing and reduced latch-up susceptibility is provided. In one aspect of the present invention, the differential input stage includes an emitter-coupled pair, a current mirror, and several series resistors. For a NPN emitter-coupled pair, a series resistor is connected between the input node and the base of each transistor of the emitter-coupled pair, and a series resistor is connected between each load resistor and its corresponding current mirror transistor. The series resistors reduce current flowing into the P interface (i.e., the bases of the emitter-coupled pair and into the emitters of the current mirror transistors) when power to the overall circuit is disabled but an input signal is present at the input terminals of the differential input stage. This reduced current in turn reduces latch-up susceptibility and, in addition, reduces power dissipation through the parasitic PNPN structures when the power to the overall circuit is disabled.
In accordance with another aspect of the present invention, each series resistor is implemented in a P-type well formed in a N-type tub. A reverse-biased diode is connected between the VCC bus and the N-type tub proximate to the P-type wells to keep the PN junction of the P-type wells reversed biased, thereby disabling the parasitic PNPN structures.